The invention relates to a method of making printed circuits and more particularly to a method of making printed circuits for use with multilayer circuit boards without mechanically pre-treating an epoxy resin surface.
When multilayer conductors are made in accordance with present prior art, the conductors are distributed over several planes, and these signal planes are laminated together with interposed prepregs and with the necessary number of power planes to form a multilayer circuit. Subsequently, the multilayer circuit is bored at predetermined places. By copper coating the through-holes a connection to the internal wiring is made. Owing to the high wiring density, particularly high demands are made today to the production of multilayer circuits with respect to the materials and methods used.
For making multilayer conductors two methods are applied. Generally, power planes are made following the subtractive method. This method uses as a starting material a copper-coated semifinished material (e.g., a glass-fiber reinforced epoxy resin foil) onto which 35 .mu.m thick copper foil is laminated on one or both sides. During processing, several copper-coated carrier plates cut to a predetermined format are pressed together to form a package, and contact holes are drilled with numerically controlled automatic units. The deburred drilled holes are throughplated and a base layer of copper is chemically deposited on the bore walls which are galvanically reinforced. The surface of the copper-coated carrier plates is subsequently prepared for the actual conductor printing by a suitable pre-treatment. The surface is coated with a photoresist and exposed in accordance with the configuration of the conductors. In a developer process, the negative photoresist can be removed in the non-exposed areas. The conductor plate then passes through an etching system which removes the copper layer where it is no longer protected by the photoresist. Subsequent to the removal of the remaining resist, only the printed circuit is left on the epoxy resin insulating layer.
A disadvantage of the substractive method is that a relatively thick copper coating has to be applied which is mostly removed again by etching. For that reason, this method is not economical for precision networks. It is therefore desirable to use a much thinner copper coating. Furthermore, the strong underetchings connected with the use of the substractive method cause a limitation of the conductor width, so that conductor widths of less than 100 .mu.m can no longer be made following this method.
For that reason, the signal planes which are used in multilayer circuits are made in accordance with another method: the additive method. The time-consuming and highly complicated additive method which is explained in detail hereinbelow, is implemented as follows. Onto a signal plane of four prepreg layers, a two-layer copper foil (5 .mu.m thick) is laminated on both sides. The approximately 70 .mu.m thick carrier foil is subsequently removed. The surface of the laminated parts is then scrubbed by means of an abrasive powder, cleaned, and dried. Then a negative photoresist is applied to increase the rigidity and a blanket exposure is carried out. After punching alignment holes, the signal plane holes are drilled, deburred and cleaned. Subsequently, the boring walls are activated with palladium chloride-tin-II-chloride and the previously applied negative photoresist is stripped off. The surface of the signal plane is processed with benzotriazole adhesion promoter and coated with a negative photoresist which is exposed image-wise and developed. In that state, the parts are immersed in a long term copper bath for approximately 20 hours. During this period, copper precipitates in the developed-out conductor channels on the approximately 5 .mu.m thick copper foil and on the boring walls up to a desired thickness of approximately 40 .mu.m. Subsequent to the building-up of the copper, a tin layer is applied on the copper lines. In the subsequent etching process, the thin copper foil is removed in those areas where there are no longer any tin-protected conductors. Then the tin layer is removed again. Finally the manufacturing process is terminated by the electrical testing of the parts after an inspection.
A decisive factor for a successful application of this method is the pre-treatment of the substrate surfaces prior to the lamination of the negative photoresist foil. An unsatisfactory resist adhesion causes the lift-off of the photoresist foil in the aggressive copper additive bath so that copper is deposited also in undesired areas, causing short-circuits in the signal lines. Repairing errors of this kind is very complicated or altogether impossible.
It is the object of the invention to provide a novel method of making multilayer circuits, which permits excellent adhesion of the photoresist foil on the substrate surface, and which eliminates a number of process steps of the above described additive method.
Essential advantages of the present invention as compared with previously known processes are that the photoresist foil can be laminated directly onto the epoxy resin surface; that all mechanical surface pre-treatments as well as all wet processes and the activation of the boring holes, the application of complicated adhesion promoters, the etching-off of the copper base foil and the application and removal of the protective tin cover of the copper conductors are no longer necessary. The copper layer applied by magnetron sputtering forms a tub-like structure onto which the copper is subsequently grown additively on three sides simultaneously, which increases the copper coating speed with conductor widths of less than 80 .mu.m. On the whole, the method as disclosed by the invention is a brief and uncomplicated process.